Using multiple traffic profiles to design a network on chip
US9294354B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | May 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application is directed to designing an efficient Network on Chip (NoC) interconnect architecture that is adaptable to varied interface protocols of different SoC components/hosts and is compliant to handle different types and models of traffic profiles. Aspects of the present application include a method, which may involve utilizing multiple traffic profiles described in a specification to generate a NoC that satisfies all the traffic profiles. Such a NoC interconnect architecture can be formed from multiple traffic profiles by generating a single consolidated traffic profile from individual or subset based dependency graphs of the multiple traffic profiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.