Fluorine passivation of dielectric for superconducting electronics
US9297067B2 · kind B2 · utility
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Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Jul 30, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/265
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (<350 C, e.g. ˜200 C) to prevent reaction with superconducting materials, then exposed to fluorine. The fluorine may be a component of a gas or plasma, or it may be a component of an interface layer. The fluorine is driven into the a-Si by heat (e.g., <350 C) or impact to passivate defects such as dangling bonds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.