Hierarchical pushdown of cells and nets to any logical depth
US9298868B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jun 19, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Jul 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.