Three-dimensional wordline sharing memory
US9299391B2 · kind B2 · utility
1Cited by
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18Claims
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Key dates
| Filing date | Jan 21, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Mar 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.