Stacked chip SPAD image sensor
US9299732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Feb 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An example imaging sensor system includes a Single-Photon Avalanche Diode (SPAD) imaging array formed in a first semiconductor layer of a first wafer. The SPAD imaging array includes an N number of pixels, each including a SPAD region formed in a front side of the first semiconductor layer. The first wafer is bonded to a second wafer at a bonding interface between a first interconnect layer of the first wafer and the second interconnect layer of the second wafer. An N number of digital counters are formed in a second semiconductor layer of the second wafer. Each of the digital counters are configured to count output pulses generated by a respective SPAD region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.