Gated III-V semiconductor structure and method
US9299821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2011 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gated III-V semiconductor structure and a method for fabricating the gated III-V semiconductor structure includes a threshold modifying dopant region within a III-V semiconductor barrier layer at the base of an aperture through a passivation layer that otherwise passivates the III-V semiconductor barrier layer. The passivation layer, which may comprise an aluminum-silicon nitride material, has particular bandgap and permittivity properties that provide for enhanced performance of a III-V semiconductor device that derives from the III-V semiconductor structure absent a field plate. The threshold modifying dopant region provides the possibility for forming both an enhancement mode gated III-V semiconductor structure and a depletion mode III-V semiconductor structure on the same substrate. The threshold modifying dopant region when comprising a magnesium (Mg) threshold modifying dopant may be incorporated into the gates III-V semiconductor structure using a dicyclopentadienyl magnesium (Cp2Mg) vapor diffusion method or a magnesium-silicon nitride (MgSiN) solid state diffusion method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.