Adaptive delay based asynchronous successive approximation analog-to-digital converter
US9300317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.