Methods for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling
US9300443B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | May 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.