Substrate structure, semiconductor package device, and manufacturing method of substrate structure
US9301391B2 · kind B2 · utility
2Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2012 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Nov 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0574
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate structure includes first, second and third metal layers embedded in a dielectric layer between its opposite upper first and lower second surfaces. The entire upper surface of the first metal layer is exposed on the first surface of the dielectric layer, the entire lower surface of the third metal layer is exposed on the second surface of the dielectric layer, and the second metal layer is disposed between the first metal layer and the third metal layer, wherein the area of the third metal layer is larger than the area of the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.