Hardware-based array compression
US9304898B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2011 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Feb 7, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described herein for compressing an array using hardware-based compression and performing various instructions on the compressed array. Some example technologies may receive an instruction adapted to access an address in an array. The technologies may determine whether address is compressible. If the address is compressible, then the technologies may determine a compressed address of a compressed array based on the address. The compressed array may represent a compressed layout of the array where a reduced size of each compressed element in the compressed array is smaller than an original size of each element in the array. The technologies may access the compressed array at the compressed address in accordance with the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.