Patent · US Active

Mixed memory type hybrid cache

US9304913B2 · kind B2 · utility

10Cited by

3References

20Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Xiangyu Dong · San Diego, US
Jungwon Suh · Apex, US

Key dates

Filing date	Mar 15, 2013
Grant date	Apr 5, 2016
Priority date	—
Expiry date	Feb 8, 2034

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A hybrid cache includes a static random access memory (SRAM) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both SRAM macros and resistive random access memory macros. The hybrid cache is configured so that the SRAM macros are accessed before the resistive random memory macros in each cache access cycle. While SRAM macros are accessed, the slower resistive random access memory reach a data access ready state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.