Patent · US Active

Instruction cache having a multi-bit way prediction mask

US9304932B2 · kind B2 · utility

0Cited by

12References

24Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Peter G. Sassone · Austin, US
Suresh K. Venkumahanti · Austin, US
Lucian Codrescu · Austin, US

Key dates

Filing date	Dec 20, 2012
Grant date	Apr 5, 2016
Priority date	—
Expiry date	Jul 5, 2034

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.