Hardware-base accelerator for managing copy-on-write of multi-level caches utilizing block copy-on-write differential update table
US9304946B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2012 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Nov 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1446
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are described herein for providing a hardware-based accelerator adapted to manage copy-on-write. Some example technologies may identify a read request adapted to read a block at an original memory address. The technologies may utilize the hardware-based accelerator to determine whether the block is located at the original memory address. When a determination is made that the block is located in at the original memory address, the technologies may utilize the hardware-based accelerator to pass the original memory address so that the read request can be performed utilizing the original memory address. When a determination is made that the block is not located in the memory at the original memory address, the technologies may utilize the hardware-based accelerator to generate a new memory address and to pass the new memory address so that the read request can be performed utilizing the new memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.