Vertical switch three-dimensional memory array
US9305624B2 · kind B2 · utility
19Cited by
15References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 20, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Jun 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. Each switch has at least three terminals and a cross-sectional area less than 6F2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.