Page buffer circuit for NAND flash memory
US9305649B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Oct 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer for a NAND flash memory array includes a pre-charge switch, a first switch, a read switch, a write switch, a latch, and a data switch. The pre-charge switch is coupled between a supply node with a supply voltage and a bit line that is coupled to a selected cell of the NAND flash memory array. The first switch is coupled between the bit line and a data node. The read switch is coupled between the data node and an I/O node. The write switch is coupled between an inverse data node, which is out of phase with the data node, and the I/O node. The latch is coupled between the data node and the inverse data node. The data switch is coupled between the inverse data node and a first node. The enable switch is coupled between the first node and a ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.