Solving MLC NAND paired page program using reduced spatial redundancy
US9305655B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reduced spatial redundancy of lower bits data provides data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory assists in restoring the data, using less than a full back up storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.