Inventor · Garden Grove, CA, US

Lan D. Phan

23Patents
10h-index
11Co-inventors
68Inventor score

Filing activity: Feb 17, 2010 → Jan 20, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US8612669B1 System and method for performing data retention in solid-state memory using copy commands and validity and usage data Physics 185 Active
US8700951B1 System and method for improving a data redundancy scheme in a solid state subsystem with additional metadata Physics 178 Active
US8316176B1 Non-volatile semiconductor memory segregating sequential data during garbage collection to reduce write amplification Emerging Cross-Sectional Technologies 173 Active
US8793429B1 Solid-state drive with reduced power up time Emerging Cross-Sectional Technologies 157 Active
US8769190B1 System and method for reducing contentions in solid-state memory access Physics 144 Active
US8713066B1 Managing wear leveling and garbage collection operations in a solid-state memory using linked lists Physics 137 Active
US8782327B1 System and method for managing execution of internal commands and host commands in a solid-state memory Physics 133 Active
US9075708B1 System and method for improving data integrity and power-on performance in storage devices Physics 14 Active
US8924629B1 Mapping table for improving write operation efficiency Physics 11 Active
US9110835B1 System and method for improving a data redundancy scheme in a solid state subsystem with additional metadata Physics 11 Active
US9170932B1 System data storage mechanism providing coherency and segmented data loading Physics 10 Active
US9135166B1 System and method for performing data retention in solid-state memory utilizing copy commands and usage data Physics 6 Active
US9652379B1 System and method for reducing contentions in solid-state memory access Physics 6 Active
US9021192B1 System and method for enhancing processing of memory access requests Physics 4 Active
US9164886B1 System and method for multistage processing in a memory storage subsystem Physics 3 Active
US10379755B2 System data storage mechanism providing coherency and segmented data loading Physics 1 Active
US9305655B2 Solving MLC NAND paired page program using reduced spatial redundancy Physics 1 Active
US9477413B2 System and method for managing access requests to a memory storage subsystem Physics 1 Active
US9875025B2 System and method for performing data retention in solid-state memory using an LRU list Physics 1 Active
US10048875B2 System and method for managing access requests to a memory storage subsystem Physics 1 Active
US9405675B1 System and method for managing execution of internal commands and host commands in a solid-state memory Physics 1 Active
US10942656B2 System data storage mechanism providing coherency and segmented data loading Physics 0 Active
US11543974B2 System data storage mechanism providing coherency and segmented data loading Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.