Fabrication method for microelectronic components and microchip inks used in electrostatic assembly
US9305807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Apr 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Charge-encoded chiplets are produced using a sacrificial metal mask and associated fabrication techniques and materials that are compatible with typical semiconductor fabrication processes to provide each chiplet with two different (i.e., positive and negative) charge polarity regions generated by associated patterned charge-inducing material structures. A first charge-inducing material having a positive charge polarity is formed on a silicon wafer over previously-fabricated integrated circuits, then a sacrificial metal mask is patterned only over a portion of the charge-inducing material structure, and a second charge-inducing material structure (e.g., a self-assembling octadecyltrichlorosilane monolayer) is deposited having a negative charge polarity. The sacrificial metal mask is then removed to expose the masked portion of the first charge-inducing material structure, thereby providing the chiplet with both a positive charge polarity region and a negative charge polarity region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.