Method of fabricating semiconductor package
US9305899B2 · kind B2 · utility
2Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2015 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.