Method for FinFET integrated with capacitor
US9305918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Sep 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides methods to fabricate a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.