Vertical NAND device containing peripheral devices on epitaxial semiconductor pedestal
US9305934B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Oct 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.