Method of manufacturing semiconductor structure
US9305993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2015 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Jan 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.