Methods of fabricating an F-RAM
US9305995B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2015 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
Abstract
Methods of forming F-RAM cells are described. The method includes forming a contact extending through a first dielectric layer on a surface of a substrate. A barrier structure is formed over the contact by depositing and patterning a barrier layer. A second dielectric layer is deposited over the patterned barrier layer and planarized to expose a top surface of the barrier structure. A ferro-stack is deposited and patterned over the barrier structure to form a ferroelectric capacitor. A bottom electrode of the ferroelectric capacitor is electrically coupled to the diffusion region of the MOS transistor through the barrier structure. The barrier layer is conductive so that a bottom electrode of the ferroelectric capacitor is electrically coupled to the contact through the barrier structure. In one embodiment, patterning barrier layer comprises concurrently forming a local interconnect (LI) on a top surface of the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.