Voltage level shifter with a low-latency voltage boost circuit
US9306553B2 · kind B2 · utility
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6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2013 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L5/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.