Method and apparatus for monitoring performance for secure chip operation
US9310862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Jun 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.