Semiconductor memory device, memory system and method of operating the same
US9311257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Nov 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips. The first memory chip, in response to the first multichip select command, receives a first operation request transmitted by the controller through the data base, and the second memory chip, in response to the second multichip select command, receives a second operation request transmitted by the controller through the data bus before the first memory chip operates according to the first operation request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.