Instruction set architecture mode dependent sub-size access of register with associated status indication
US9317285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2012 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Feb 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.