Patent · US Active

Generation of instruction set from architecture description

US9317298B2 · kind B2 · utility

1Cited by
11References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 22, 2013
Grant dateApr 19, 2016
Priority date
Expiry dateNov 3, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F8/76
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Generating an instruction set for an architecture. A hierarchical description of an architecture is accessed. Groups in the hierarchical description that can be pre-encoded without increasing final width of said instruction set are pre-encoded. The hierarchical description is permutated into a plurality of variations. Each variation comprises a leaf-group and one or more sub-graphs to be encoded. For each said variation, the leaf-group and the one or more sub-graphs are encoded to produce a potential instruction set for each variation. One of the potential instruction sets is selected.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.