Apparatus and method for controlling the reliability stress rate on a processor
US9317389B2 · kind B2 · utility
1Cited by
24References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Oct 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3058
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.