Methods and apparatus related to data processors and caches incorporated in data processors
US9317448B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Jul 30, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | May 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.