Dual asynchronous and synchronous memory system

US9318171B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gary A. Van Huben · Poughkeepsie, US
• Patrick J. Meaney · Poughkeepsie, US
• John S. Dodson · Pflugerville, US
• Scot H. Rider · Pleasant Valley, US
• James C. Gregerson · Hyde Park, US
• Eric E. Retter · Austin, US
• Irving G. Baysah · Hutto, US
• Glenn D. Gilda · Binghamton, US
• Lawrence D. Curley · Endwell, US
• Vesselina K. Papazova · Highland, US

Key dates

• Filing date: Sep 30, 2014
• Grant date: Apr 19, 2016
• Expiry date: Nov 25, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4076
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.