Method for operating small-area EEPROM array
US9318208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.