Methods of forming vertical cell semiconductor devices with single-crystalline channel structures
US9318329B2 · kind B2 · utility
4Cited by
4References
16Claims
0Family size
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Key dates
| Filing date | May 7, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | May 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.