Wafer level package without sidewall cracking
US9318405B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2015 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | May 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer. The molding compound may eliminate sidewall chipping and cracking as well as reduce the need for back side lamination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.