Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9318411B2 · kind B2 · utility
10Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Oct 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.