Chip stack packages, system in packages including the same, and methods of operating the same
US9318420B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2012 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package including a first semiconductor chip and second semiconductor chip, the first semiconductor chip including first data I/O pads for transmitting data I/O signals, a first flag pad for receiving a flag signal, and a first buffer for controlling a switching operation between the first data I/O pads and an internal circuit of the first semiconductor chip. The second semiconductor chip includes second data I/O pads for transmitting the data I/O signals, a second flag pad for receiving the flag signal, and a second buffer for controlling a switching operation between the second data I/O pads and an internal circuit of the second semiconductor chip. The first data I/O pads are electrically connected to respective ones of the second data I/O pads through first wires, and the first flag pad is electrically connected to the second flag pad through a second wire. Related methods are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.