Integrated structure in wafer level package
US9318429B2 · kind B2 · utility
25Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jun 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/92244
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment device package includes a die having a conductive pillar and a molding compound extending along sidewalls of the die. The molding compound at least partially covers a top surface of the die. The device package further includes a conductive via extending through the molding compound and a redistribution layer (RDL) over the molding compound. The RDL and the molding compound have a continuous interface extending from the conductive via to a point over the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.