Fin-type PIN diode array
US9318622B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2015 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jun 23, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and methods of manufacturing a fin-type PIN diode array include forming a plurality of first charge-type doped silicon fins disposed in parallel on a planar substrate in a first direction, forming undoped epitaxial growths of silicon at intervals along a length of each silicon fin, where each epitaxial growth includes a depleted intrinsic region, and forming a plurality of second charge-type doped polysilicon fins disposed in parallel and disposed perpendicularly to the first direction. The polysilicon fins are formed to contact, at intervals along a length of each polysilicon fin, an uppermost surface of one of the undoped epitaxial growths of silicon, to form a PIN diode at each intersection of each of the first charge-type doped silicon fins and the second charge-type doped polysilicon fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.