Robert R. Robison
146Patents
8h-index
117Co-inventors
79Inventor score
Filing activity: Mar 13, 2008 → Jul 26, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9859421B1 | Vertical field effect transistor with subway etch replacement metal gate | Electricity | 23 | Active |
| US9728466B1 | Vertical field effect transistors with metallic source/drain regions | Electricity | 18 | Active |
| US9530798B1 | High performance heat shields with reduced capacitance | Electricity | 12 | Active |
| US9318622B1 | Fin-type PIN diode array | Emerging Cross-Sectional Technologies | 10 | Active |
| US10096607B1 | Three-dimensional stacked junctionless channels for dense SRAM | Electricity | 10 | Active |
| US10170584B2 | Nanosheet field effect transistors with partial inside spacers | Electricity | 9 | Active |
| US9240406B2 | Precision trench capacitor | Electricity | 8 | Active |
| US8685817B1 | Metal gate structures for CMOS transistor devices having reduced parasitic capacitance | Electricity | 8 | Active |
| US8815669B2 | Metal gate structures for CMOS transistor devices having reduced parasitic capacitance | Electricity | 7 | Active |
| US8361872B2 | High performance low power bulk FET device and method of manufacture | Electricity | 7 | Active |
| US9059203B2 | Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure | Electricity | 6 | Active |
| US10128347B2 | Gate-all-around field effect transistor having multiple threshold voltages | Electricity | 6 | Active |
| US8610211B2 | Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure | Electricity | 5 | Active |
| US8110483B2 | Forming an extremely thin semiconductor-on-insulator (ETSOI) layer | Electricity | 5 | Active |
| US9911804B1 | Vertical fin field effect transistor with air gap spacers | Electricity | 5 | Active |
| US10170485B2 | Three-dimensional stacked junctionless channels for dense SRAM | Electricity | 4 | Active |
| US8686508B2 | Structures, methods and applications for electrical pulse anneal processes | Electricity | 4 | Active |
| US8530319B2 | Vertical silicide e-fuse | Electricity | 4 | Active |
| US8053870B2 | Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure | Electricity | 4 | Active |
| US10381437B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 4 | Active |
| US8486796B2 | Thin film resistors and methods of manufacture | Electricity | 4 | Active |
| US8017489B2 | Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed | Electricity | 4 | Active |
| US9917196B1 | Semiconductor device and method of forming the semiconductor device | Electricity | 4 | Active |
| US8470682B2 | Methods and structures for increased thermal dissipation of thin film resistors | Electricity | 3 | Active |
| US8637871B2 | Asymmetric hetero-structure FET and method of manufacture | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.