Resistive memory cell having a reduced conductive path area
US9318702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Feb 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.