Patent · US Active

Integrated circuit failure prediction using clock duty cycle recording and analysis

US9319030B2 · kind B2 · utility

0Cited by

11References

19Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Thomas Gentner · Eppelheim, DE
Klaus P. Gungl · Sindelfingen, DE
Guenther Hutzl · Sindelfingen, DE

Key dates

Filing date	Dec 12, 2013
Grant date	Apr 19, 2016
Priority date	—
Expiry date	Jun 27, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1565
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A system is disclosed, which may include a clock distribution circuit. The clock distribution circuit may include a duty cycle controller to distribute a clock output signal to a plurality of remote locations on a clock grid. The duty cycle controller may adjust, in response to a duty cycle control signal, a duty cycle of the clock output signal. The clock distribution circuit may also include a duty cycle measurement unit, to measure the duty cycle of the clock output signal at one of the remote locations, generate the duty cycle control signal, and generate and write duty cycle data values to a memory unit. The system may also include control logic to calculate and transmit a clock distribution circuit end-of-life date, by applying a model to stored duty cycle data values and to a duty cycle controller adjustment state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.