Phase-locked loop (PLL)
US9319053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jul 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.