Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
US9319073B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jun 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.