Method of manufacturing a component-embedded substrate
US9320185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2010 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jul 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09918
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A thin conductive layer which is to form a conductor pattern (18) is prepared, a mask layer (3) is formed on the conductive layer except a plurality of actual connection spots and at least one dummy connection spot on the conductive layer, actual solder pads (6) and a dummy solder pad (7) are formed, with use of solder, on the actual connection spots and the dummy connection spot, respectively, where the conductive layer is exposed, connection terminals (9) of an electric or electronic component (8) are connected to the actual solder pads (6), an insulating base (16) of resin is formed which is laminated directly on or indirectly via the mask layer (3) on the conductive layer and in which the component (8) is embedded, and part of the conductive layer is removed by using the dummy solder pad (7) as a reference, to form the conductor pattern (18).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.