Monitoring vector lane duty cycle for dynamic optimization
US9323525B2 · kind B2 · utility
11Cited by
24References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a vector execution unit having a plurality of lanes to execute operations on vector operands, a performance monitor coupled to the vector execution unit to maintain information regarding an activity level of the lanes, and a control logic coupled to the performance monitor to control power consumption of the vector execution unit based at least in part on the activity level of at least some of the lanes. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.