Performance of emerging applications in a virtualized environment using transient instruction streams
US9323527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2010 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Dec 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.