Method and apparatus to represent a processor context with fewer bits
US9323715B2 · kind B2 · utility
1Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2013 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Apr 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers are employed to probe, or access, one or more structures of the processor device in executing an operation associated with a computer process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.