Patent · US Active

System and method for a level shifting decoder

US9324399B2 · kind B2 · utility

4Cited by

2References

29Claims

0Family size

Assignees

STMicroelectronics International N.V. · NL
STMicroelectronics SA

Inventors

Marco Pasotti · Pavia, IT
Abhishek Lal · Faridabad, IN
Rajat Kulshrestha · Noida, IN

Key dates

Filing date	Feb 18, 2014
Grant date	Apr 26, 2016
Priority date	—
Expiry date	Aug 23, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.