CMOS analog memories utilizing ferroelectric capacitors
US9324405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.