Write assist circuit, memory device and method
US9324413B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Oct 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.